Manufacturing processes of a field-effect transistor constituting an integrated circuit formed in a semiconductor region will be described with reference to FIG. 1, using an LDD (Lightly Doped Drain)-structure n-type field-effect transistor as an example.
At first, element isolation is carried out, for example, by an STI (Shallow Trench Isolation) method, thereby forming an element region 102 on the surface of a p-type (110) surface silicon 101 serving as a semiconductor substrate (FIG. 1(a)).
Pre-oxidation cleaning such as RCA cleaning is applied to the element region 102 (FIG. 1(b)) to remove organic compounds, particles, and metal impurities and, thereafter, dilute hydrofluoric acid treatment and then rinsing with pure water are performed to hydrogen-terminate 103 the element region 102 (FIG. 1(c)). After drying the wafer (FIG. 1(d)), a gate insulating film (SiO2) 105 is formed (FIG. 1(e)).
Then, boron is ion-implanted over the entire surface of the silicon 101 for controlling the threshold voltage (FIG. 1(f)).
Then, a polycrystalline silicon film is deposited over the entire surface of the silicon 101 and then patterned, thereby forming a gate electrode 106 of polycrystalline silicon on the gate insulating film 105 in the element region 102 (FIG. 1(g)).
Then, phosphorus is ion-implanted at a low concentration, thereby forming n− source and drain regions 107 that serve to relax high electric fields (FIG. 1(h)).
Then, a silicon oxide film (SiO2) is deposited over the entire surface of the silicon 101 by a CVD method or the like so as to cover the gate electrode 106 and then anisotropic etching is performed, thereby forming a side-wall insulating film 108 on the side walls of the gate electrode 106 (FIG. 1(i)).
Thereafter, n-type impurities such as arsenic are ion-implanted at a high concentration, thereby forming n+ source and drain regions 109 (FIG. 1(j)).
In Patent Document 1, the present inventors have previously proposed a semiconductor device manufacturing method that uses H2O added with hydrogen or deuterium and applies high-frequency vibration when cleaning a semiconductor surface, thereby performing hydrogen termination thereof.
Herein, when forming the field-effect transistor as described above on the Si (110) surface or Si (111) surface or further on polycrystalline Si, it takes time to perform the dilute hydrofluoric acid treatment to achieve the hydrogen termination 103 in FIG. 1(d). Speaking of the time required for stripping a chemical SiO2, formed in the RCA cleaning, by the dilute hydrofluoric acid treatment to achieve the hydrogen termination, it can be realized by immersion in a 0.5 wt % dilute hydrofluoric acid solution for 1 minute or so in the case of the Si (100) surface. However, in the case of the Si (110) surface, the Si (111) surface, or further the polycrystalline Si, it is necessary to immerse it in a 0.5 wt % dilute hydrofluoric acid solution for 10 minutes or more. In order to shorten the hydrogen termination time to about 3 minutes, it is necessary to increase the concentration of the dilute hydrofluoric acid by approximately 10 wt %. In this case, a silicon oxide film used in the STI is etched particularly at its embedded central portion, so that a void 104 is formed as shown in FIG. 1(c). In the later gate electrode forming process (FIG. 1(g)), the polycrystalline silicon is embedded in the void 104. When the integrated circuit is completed, this polycrystalline silicon embedded in the void 104 causes deterioration of withstand voltage between the elements and further causes occurrence of wiring shorts.
In three-dimensional transistors such as Fin-FETs, there is a case where one transistor is formed on both Si (100) and (110) surfaces.
FIG. 2 shows states before and after formation of a gate insulating film of a Fin-FET. FIG. 2(a) is a section of an element region as seen in a direction from source to drain. SiO2 202 is formed on a Si substrate 201 and a Fin 203 is formed thereon. The element region comprises a Si (100) surface 204 and Si (110) surfaces 205. After performing acid cleaning (HCI/H2O2 cleaning) in RCA cleaning, a chemical oxide film 206 is formed (FIG. 2(b)). Thereafter, 0.5 wt % dilute hydrofluoric acid treatment is carried out to strip the chemical oxide film 206, but it takes about 10 minutes to hydrogen-terminate the Si (110) surfaces 205. By the treatment for about 10 minutes, etching of an STI silicon oxide film proceeds like in the case of FIG. 1, thus causing deterioration of withstand voltage between elements and wiring shorts. Hydrogen termination of the Si (100) surface 204 is completed in 1 minute or so, but, thereafter, the Si (100) surface 204 is overetched for 9 minutes until the hydrogen termination of the Si (110) surfaces 205 is accomplished. This causes a bad effect that the Si (100) surface is roughened (207 in FIG. 2(c)). As a result, the electric reliability of a gate insulating film 208 formed on the Si (100) surface 204 is inferior to that of a gate insulating film 209 formed on the Si (110) surfaces 205 (FIG. 2(d)).
On the other hand, Patent Document 1 discloses the hydrogen termination in the cleaning process, but gives no explanation about the hydrogen termination when stripping the chemical oxide film by carrying out the dilute hydrofluoric acid treatment.    Patent Document 1: Japanese Unexamined Patent Application Publication (JP-A) No. 2005-51141